
What we’re about
This is a location for Startups, Events, Lectures, Hackathons, DevHouses, tinkering, brainstorming, co-working, and more! We have events occurring on a daily basis @hackerdojo.org
Upcoming events (4+)
See all- DATA STRUCTURES & ALGORITHMS STUDY GROUPHacker Dojo, Mountain View, CA
Join our biweekly data structures & algorithms study group! Explore DSA topics, practice problem-solving, and sharpen your coding skills for technical interviews.
Attendance is free and open to the public. These sessions are in-person only.
This week’s topic: TBD
The first hour will include a brief overview of the week’s topic, some example problem walkthroughs, and extra support for beginners. Code examples will typically be in Python.
If you are already comfortable with the topic, feel free to skip the talks/tutorials and come join us at any point during problem-solving time.
Join us on Discord: https://discord.gg/z4vvatsz9z
- Making a break into Venture CapitalHacker Dojo, Mountain View, CA
Join Founders Creative for a live session on investing in AI startups.
We will discuss the state of the industry and investing, how to evaluate startups, and how to invest in the next generation of AI unicorns.
This session is only for accredited investors who invest or intend to invest at least a $100K (over four years) in a venture fund.
SEC definition of accreditation:- Net worth over $1 million, excluding primary residence (individually or with spouse or partner)
OR
- Income over $200,000 (individually) or $300,000 (with spouse or partner) in each of the prior two years, and reasonably expects the same for the current year
https://www.sec.gov/resources-small-businesses/capital-raising-building-blocks/accredited-investors
- Verilog MeetupHacker Dojo, Mountain View, CA
Verilog Meetup
We continue to work on developing hands-on exercises and educational
materials that include:- Tutorial-level examples working on FPGA boards from multiple
vendors - Xilinx, Altera, Gowin, Lattice, Efinix. - More involving examples with sound recognition and graphics generation.
- Interview-level microarchitectural examples with pipelines, FIFOs
and flow control. - CPU-oriented exercises, from a trivial single-cycle CPU to
pipelined, out-of-order and multicore designs with caches and branch
predictors. - Experiments with open-source ASIC design tools and the affordable
manufacturing options (Tiny Tapeout).
For more information see https://verilog-meetup.com
Thank you,
Yuri Panchul - Tutorial-level examples working on FPGA boards from multiple